今天對PLL中areset和locked詳細(xì)查了下資料,，發(fā)現(xiàn)網(wǎng)上這方面的資料很少，所以自己認(rèn)真讀了下Documentation---ug_altpll.pdf,現(xiàn)在我將我學(xué)到的內(nèi)容總結(jié)如下：

        areset簡而言之就是高電平有效,，對pll進(jìn)行復(fù)位,。

        下面我們主要來認(rèn)識一下locked信號：

        Locked這個輸出到底是干嘛用的呢，pdf中這樣寫道：

        The ALTPLL megafunction allows you to monitor the PLL locking process using a lock signal named locked and also allows you to set the PLL to self-reset on loss of lock.

        原來這Locked信號是用來觀察pll輸出時鐘是否和輸入時鐘鎖定,。當(dāng)鎖定時,，這個Locked信號就變?yōu)楦唠娖健?/p>

        但pdf中又這么寫道：

        The locked signal might toggle as the PLL begins tracking the
reference clock. To avoid such a false lock indication, use a gated lock signal.

        當(dāng)這個pll剛開始跟蹤輸入時鐘時這個Locked信號又可能會發(fā)生跳轉(zhuǎn)，為了避免這種錯誤的指示,，我們就使用gated lock信號。這個gated lock信號其實(shí)和locked信號是同一個,，locked信號多了個計數(shù)功能后就叫做gated lock了,。

        You must specify the number of PLL input clock cycles to hold the locked
signal low after the PLL is initialized

就是在pll被初始化之后，讓gated lock依舊保持低電平多少個周期,，以此來解決下面圖片中的問題：

        這圖片中l(wèi)ocked在pll開始跟蹤輸入時鐘的時候一直在抖動,，而gated lock因為設(shè)置了上面周期后，開始階段始終為low,，直到到達(dá)counter值后變?yōu)楦唠娖?，這就避免了locked的抖動。所以gated lock信號更加穩(wěn)定,。

        這個時鐘周期怎么算呢,，如下:

        To calculate the number of clock cycles needed, you must know the maximum lock time of the PLL, and the period of the PLL input clock. The lock time of the PLL is listed in the “PLL Timing Specifications” section of the DC & SwitchingCharacteristics chapter of the device handbook. The period of the PLL input clock is user-specified. For example, if the maximum lock time of a PLL is 1ms,and its input clock frequency is 100 MHz which corresponds to a 10 ns clock period, you calculate the value of the gated lock counter, by dividing 1 ms by 10 ns. The result is 100,000 clock cycles. 這個我就不解釋了，大家自己看吧,，很容易理解的,。

        不同器件類型對gated lock和self-reset的支持情況不一樣

不足之處還望大家多多指出啊~~